1. Field of the Invention
The present invention relates generally to multi-banked dynamic random access memory (DRAM) devices and more specifically to a hierarchical row selection method and circuit for local activation of a memory array block.
2. Description of the Related Art
FIG. 1A shows the configuration of a multiple bank 1 Gbit DRAM integrated circuit chip for purposes of illustration. This DRAM chip is not admitted to be prior art. The chip consists of eight 128 Mb double units 11. Four 128 Mb double units 11 are arranged in each top and bottom half of the DRAM chip. The peripheral circuits 15 are located between the top and the bottom of the chip, where a plurality of address lines (i.e. 16 row address lines), a data bus (i.e. 32 data for xc3x9732 organization), and control signals are arranged. These signals control the eight 128 Mb double-units 11 for data read and write operations. The 128 Mb double unit 11 includes two 64 Mb units 14, a row decoder block (RDEC 10), column decoder block (CDEC) 12, and address pre-decoder block (PDEC) 13.
FIG. 1B is a detailed block diagram showing a portion of the 128 Mb double unit, in which the right 64 Mb unit and CDEC 12 are not shown for ease of illustration and explanation. The 64 Mb unit includes a plurality of the blocks 16 (e.g. 16 blocks of 4 Mb capacity each). Each block 16 includes a plurality of memory cells (for example, each block contains 4 M cells) which are arranged in x rows (e.g. 1024 rows) by y columns (e.g. 4096 columns) as is conventional in a memory array. Cells arranged in each row are coupled to the corresponding one-out-of-x wordlines (WLs), which is decoded by the corresponding one-out-of-x row decoders (RDECs) 10A. The RDEC 10A is driven by the predecoded addresses 22, the drivers of which are located at the PDEC 13. Sense amplifiers (SA) 18 are located between the adjacent blocks 16.
FIG. 1C is a block and circuit schematic showing a memory cell 21 within block 16, its connection to SA 18 and the transistors which make up RDEC 10A which drives the wordline (WL). For ease of illustration, the wordline driver has not been shown in FIG. 1C.
The read mode operation of the circuit shown in FIG. 1B will now be described. When the row address strobe (RAS) signal (not shown) is enabled, the peripheral circuits 15 drive addresses 20. The addresses 20 are predecoded by the PDEC 13, which drives the predecoded addresses 22. The block select signal (BLKSEL) triggers the activation of the WL by enabling RDEC 10A. When the predecoded addresses 22 are enabled for a particular RDEC 10A, upon receipt of the enabled BLKSEL at the RDEC 10A, signals which activate the corresponding WL is provided to the WL driver (not shown). With the RDEC circuit scheme shown in FIGS. 1B and 1C, the time at which the WL starts to rise and the time at which the WL starts to fall are controlled by the leveled block select signal BLKSEL.
The BLKSEL signal is also used to activate SA 18 at a controlled time after the activation of the WL to latch the data on a complementary bitline pair (BL,/BL). An independent BLKSEL signal is generated for each block 16. Generating the BLKSEL signal is therefore the key to controlling the block 16 to activate the WL and the SA 18 at their proper respective times.
FIG. 2A is a block diagram showing a circuit arrangement in which predecoded addresses 22 are used as the BLKSEL signal. Such arrangement is described in detail in the article by Y. Watanabe et al entitled xe2x80x9cA 286 mm2256 Mb DRAM with xc3x9732 Both-Ends DQ,xe2x80x9d JSSC, Vol. 31, No. 4, April 1996, pp. 567-574. The 64 Mb unit 14 includes sixteen 4 Mb blocks 16, each block which includes 1024 WLs. In order to select and activate one wordline out of the 16,384 wordlines in the 64 Mb unit (sixteen blocks per unit xc3x971024 WLs per block), 14 address signals ADD less than 0:13 greater than  are used, where the most significant four address signals ADD less than 10:13 greater than  are assigned to generate the sixteen predecoded addresses. These sixteen predecoded addresses generated from ADD less than 10:13 greater than  are used as the BLKSEL signals to respective ones of each of the sixteen blocks 16.
The predecoded BLKSEL scheme shown in FIG. 2A requires that the number of signal conductors carrying predecoded addresses 22 be increased as the number of the blocks 16 increases within the 64 Mb unit. Thirty-two BLKSEL signal conductors are required for the 128 Mb double unit 11, requiring an area of approximately 100 um2, which is almost one quarter the area of the row decoder block 10.
The scheme shown in FIG. 2A also requires that other predecoded addresses 22 be held in an enabled state if one of the thirty-two blocks 16 is to be activated. With such signaling scheme, it is difficult to configure the memory with multiple banks. Multi-bank organization requires that blocks be controlled independently. However, the existing signaling scheme, which requires separate predecoded address lines for each bank, requires too many signal conductors, and is therefore not practical. Thus, the existing signaling scheme is practical only for a single bank design within a 128 Mb double unit 11.
FIG. 2B is a block diagram showing a shared row decoder (SRDEC) 10B which allows the predecoded addresses 24 to be shared within two 64 Mb units 14l and 14r. The predecoded addresses 24 are used to generate the BLKSEL signals. This is referred to as a predecoded block select (BLKSEL) scheme. However, the time at which the wordline (WL) starts to rise is controlled by a local block select signal (LBLKSEL) in the form of a self-resetting pulse which is triggered by BLKSEL.
The LBLKSEL signal triggers the latching of the decoded address in the SRDEC 10B. The shared predecoded address signal lines 24 can then be used to access storage locations within the other bank. The time at which the wordline falls is controlled as in the predecoded BLKSEL approach. This makes is possible to configure the left and right 64 Mb units 14l and 14r as banks 0 and 1, respectively. However, this scheme has a similar problem to that of the decoding scheme shown in FIG. 2A in that the number of BLKSEL signal lines increases as the number of blocks 16 increases. In addition, the BLKSEL approach does not permit more than two banks to be configured within a single left or right unit, e.g. within either left or right 64 Mb unit shown in FIG. 2B.
When the principle of reducing the number of timing lines shown in FIG. 2B is applied to a single unit containing multiple banks, a problem arises in that individual banks cannot be reset at different times. This is illustrated in the timing diagram shown in FIG. 2C. When the precharge signal /PRG is activated, all blocks 16 are reset upon the falling edge 25 of /PRG, even though more than one bank is configured within the unit. Such simultaneous resetting contradicts the requirement that every bank be individually activated (set) and precharged (reset). The invention which will be described below overcomes this problem and allows the precharge signal to be controlled separately for each bank of a multiple bank unit of a DRAM.
By contrast, in the present invention described below, there is no limit to the number of banks which can be configured within a single left or right memory unit, for example the right 64 Mb unit 14r shown in FIG. 2B. Moreover, the invention described in the following provides a way to reduce the total number of required predecoded address signal lines irrespective of the number of blocks configured within a single left or right memory unit.
Accordingly, it is an object of the present invention to provide a method of activating a wordline in a hierarchical manner.
Another object of the invention is to provide a circuit which activates a local block within a double unit 11 of a memory in a hierarchical manner.
Another object of the invention is to permit the independent activation and resetting of individual banks within a multi-bank DRAM.
The inventive bank selection method and circuit adopt a hierarchical banking control concept for local activation of a block within a chip""s double unit 11. This activation is achieved by reducing the total number of Wordline (WL) activation timing signals that are required to raise and reset the WL in each memory array bank.
More specifically, the invention proposes a structure of the double unit 11 including a plurality of banks, each of the banks including a plurality of blocks, a plurality of dedicated bank address lines carrying leveled WL activation timing information (with the high state for WL high and the low state for WL low) connected to all of the blocks in respective ones of the banks (the number of the dedicated bank address lines being equal to or more than the number of the banks in the double unit 11), and a plurality of shared address lines connected to all or at least two of the blocks in the double unit 11.
The dedicated bank address lines containing leveled WL activation timing information identify a selected bank. The shared address lines identify the selected block within the selected bank and a particular wordline within a block. The shared address lines are shared between at least two blocks in at least two different banks in the double unit 11.
Each of the blocks includes a conditional receiving latch circuit (CRLC) to generate a leveled block select signal LBLKSEL, which passes the leveled WL activation timing information carried on the respective one of the bank address lines, if the respective one of the decoded block address is valid during the set phase (low to high on the respective one of the bank address lines). Once activated, the reset timing of LBLKSEL depends only on the reset timing of the respective one of the bank address lines. Each of the blocks also includes a plurality of the row decoder circuits receiving the WL activation timing information from the latch circuit CRLC and shared row information from the respective one of the shared row address lines.
The address lines to select a particular word line in a block are shared between at least two blocks in at least two different banks within the double unit 11, and each of the blocks drives a plurality of wordlines. The shared address lines may have a certain degree of decoding done at the predecoders PDEC 13.
With the invention, timing information is transferred from one bank hierarchy to the next on predecoded/scrambled addresses. This allows the invention to use only one dedicated predecoded bank address line carrying leveled WL activation timing information per bank in the multibank DRAM architecture and to multiplex other non-timing predecoded addresses in the row path for local block descrambling.
Thus, the invention reduces the number of critical timing signal lines which conventionally run all the way from the row decoder to each memory block (for a distance of about 8 mm in the example discussed above). Conventionally there may be up to 320 of these lines (i.e. 10 address lines for each of the 32 blocks in the double unit). The invention reduces the number to 4, by multiplexing the timing information onto just 4 combined address/timing information lines (e.g., lines 300-350 in FIG. 3), and perform a local demultiplexing operation with a block selection signal.
Since the rest of the predecoded address signals (e.g., lines 310 in FIG. 3), which are required to activate every 2 Mb block, do not carry any timing-related data, they can be shared between several banks. These addresses are multiplexed into just 5 signals (log2 32) and descrambled in the Row Control portion of the chip using the decoding circuit shown in FIG. 4. Thus, with the invention, the conventional area penalty required to drive slow timing-carrying signals to each of the blocks is eliminated and the row decoder""s performance is improved.
In summary, the present invention is directed to a memory structure having hierarchical bank control, said structure comprising:
a plurality of banks, each of said banks including a plurality, of blocks;
a plurality of predecoded bank timing critical address lines that carry block activation timing information, said predecoded bank timing critical address lines being connected to different ones of said banks and being connected to all of said blocks within a respective bank of said banks, a number of said predecoded bank timing critical address lines being equal to a number of said banks; and
a plurality of dedicated address lines connected to respective ones of said blocks.
The memory structure in accordance with the present invention further comprises a plurality of shared address lines connected to all of said blocks.
Also, in accordance with the present invention, said timing critical address lines identify a selected bank having a selected block.
In another aspect of the present invention, said dedicated address lines and said shared address lines identify said selected block within said selected bank.
Further in accordance with the present invention, each of said blocks includes a self-timed latch circuit connected to a respective one of said predecoded bank timing critical address lines. In another aspect according to the present invention, each of said blocks includes a shared row decoder circuit receiving timing information from said conditional receiving latch circuit and row information from a respective one of said dedicated address lines. In accordance with another aspect of the present invention, a number of said dedicated address lines is equal to a number of said blocks. According to another aspect of the present invention, each of said blocks drives a plurality of wordlines and said memory structure comprises a dynamic random access memory structure.